PIC18F4682T-I/ML【PDF 7/183 页】IC PIC MCU FLASH 40KX16 44QFN

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PIC18F46J50 FAMILY

DS39931D-page 104

2011 Microchip Technology Inc.

FIGURE 7-2:

TABLE WRITE OPERATION

7.2

Control Registers

Several control registers are used in conjunction with

the TBLRD and TBLWT instructions. Those are:

EECON1 register

EECON2 register

TABLAT register

TBLPTR registers

7.2.1

EECON1 AND EECON2 REGISTERS

The EECON1 register (Register 7-1) is the control

not a physical register; it is used exclusively in the

memory write and erase sequences. Reading

EECON2 will read all ‘0’s.

The WPROG bit, when set, will allow programming

two bytes per word on the execution of the WR

command. If this bit is cleared, the WR command will

result in programming on a block of 64 bytes.

The FREE bit, when set, will allow a program memory

erase operation. When FREE is set, the erase

operation is initiated on the next WR command. When

FREE is clear, only writes are enabled.

The WREN bit, when set, will allow a write operation.

On power-up, the WREN bit is clear. The WRERR bit is

set in hardware when the WR bit is set and cleared

when the internal programming timer expires and the

write operation is complete.

The WR control bit initiates write operations. The bit

cannot be cleared, only set, in software. It is cleared in

hardware at the completion of the write operation.

Table Pointer(1)

Table Latch (8-bit)

TBLPTRH

TBLPTRL

TABLAT

Program Memory

(TBLPTR)

TBLPTRU

Instruction: TBLWT*

Note

The Table Pointer actually points to one of 64 holding registers, the address of which is determined by

TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in

Section 7.5 “Writing to Flash Program Memory”

Holding Registers

Program Memory

Note:

During normal operation, the WRERR is

read as ‘1’. This can indicate that a write

operation was prematurely terminated by

a Reset, or a write operation was

attempted improperly.

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